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Pipelined MIPS Processor Design

Son Teslim Tarihi: 17 Mayıs 2019 23:00
Bütçe: ~40 TL
Bilgisayar Bilgisayar Yazılım Kodlama Kod
Pipelined MIPS Processor Design

1. Download and install ModelSim Altera Starter Edition for Verilog compilation and simulation:
https://www.intel.com/content/www/us/en/programmable/downloads/software/service-packs/sps-modelsim-starter.html
Alternative:
https://www.mentor.com/company/higher_ed/modelsim-student-edition
2. Introduction video
Part 1
https://www.youtube.com/watch?v=6M79Mb7OnM0
Part 2
https://www.youtube.com/watch?v=03qZHYXv5rY
3. Introduction from another lecturer:
https://www.youtube.com/watch?v=Z8whdGa7RtY
4. Download pipelined MIPS processor design with testbench and test instructions in instruction memory module from GitHub:
https://github.com/mhyousefi/MIPS-pipeline-processor
5. Start a project and add all necessary Verilog modules and testbench to your project.
6. Compile all.
7. Simulate the testbench (Library  Work  testbench)

Assignments
1. (20 points) Open the wave viewer and show how an addi (add immediate) instruction works. How is it loaded form instruction memory? How does it flow in the pipeline? How are the operands added in the ALU? How is the result written to the register file? You can use multiple screenshots and mark the flow using the Paint program and put in your report.

2. (20 points) Illustrate how a ld (load) instruction works. How is it loaded form instruction memory? How does it flow in the pipeline? How the data is taken from data memory? How is it written to register file?

3. (60 points) The chart below shows how BNE r2, r1, -15 (branch not equal) works when the branch is taken.

The instruction takes 2 clock cycles. “Predict branches as not taken” approach is implemented in this design. We see that the backward branch causes to flush one invalid instruction.

Implement “Predict backward branches taken, forward branches not taken” approach. Do the implementation in IF stage. A branch is backward when its offset is negative, and it is forward when its offset is positive.

The prediction is understood to be false or true in ID stage. You should flush the invalid instructions if your prediction is false. In the provided code, a mechanism to flush invalid instructions is already included.

Show that after you change the design BNE r2, r1, -15 takes only 1 clock cycle like the other instructions, when the prediction is correct.

Show how you flush incorrect predictions.

You can add instructions to the instruction memory to show correct operation of your design. Make sure that there is no data hazard for your branch instruction. Data hazards may cause extra stalls in the processor.
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